Computer scientists author book on hardware prefetching
Professor Thomas F. Wenisch and his collaborator Prof. Babak Falsafi of EPFL Switzerland have authored a new book entitled “A Primer on Hardware Prefetching,” which has been published by Morgan & Claypool as one of their Synthesis Lectures on Computer Architecture.
The book describes how, since the 1970’s, microprocessor-based digital platforms have been riding Moore’s law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution rate, memory fabrication technologies have focused primarily on an increase in capacity with negligible increase in speed. This divergent trend in performance between the processors and memory has led to a phenomenon referred to as the “Memory Wall.”
To overcome the memory wall, designers have resorted to a hierarchy of cache memory levels, which rely on the principal of memory access locality to reduce the observed memory access time and the performance gap between processors and memory. Unfortunately, important workload classes exhibit adverse memory access patterns that baffle the simple policies built into modern cache hierarchies to move instructions and data across cache levels. As such, processors often spend much time idling upon a demand fetch of memory blocks that miss in higher cache levels. Prefetching – predicting future memory accesses and issuing requests for the corresponding memory blocks in advance of explicit accesses – is an effective approach to hide memory access latency. There have been a myriad of proposed prefetching techniques, and nearly every modern processor includes some hardware prefetching mechanisms targeting simple and regular memory access patterns. This primer offers an overview of the various classes of hardware prefetchers for instructions and data proposed in the research literature, and presents examples of techniques incorporated into modern microprocessors.
Prof. Wenisch received his PhD in electrical and computer engineering from Carnegie Mellon University in 2007 and joined the faculty at Michigan that year. His research is focused on high-performance computer architecture with particular emphasis on energy/power efficiency, data center architecture, smartphone/handheld architecture, memory systems, and performance evaluation methodology.
Prof. Wenisch was the recipient of an NSF CAREER award in 2009 and was named a Morris Wellman Faculty Development Assistant Professor of EECS in 2011. He was recognized in the International Symposium of Computer Architecture Hall of Fame in 2011 for having eight or more papers in ISCA. In 2013, he received the University of Michigan Henry Russel Award, which is bestowed upon faculty members early in their academic careers who have already demonstrated an extraordinary record of accomplishment in scholarly research and/or creativity, as well as an excellent record of contribution as a teacher.